/*******************************************************************************
 *                                    ZLG
 *                         ----------------------------
 *                         innovating embedded platform
 *
 * Copyright (c) 2001-present Guangzhou ZHIYUAN Electronics Co., Ltd.
 * All rights reserved.
 *
 * Contact information:
 * web site:    https://www.zlg.cn
 *******************************************************************************/
#ifndef __HPM6E00_REGS_UART_H
#define __HPM6E00_REGS_UART_H

#ifdef __cplusplus
extern "C" {
#endif  /* __cplusplus*/

#include "core/include/hpm6e00_regs_base.h"
#include <stdint.h>

/* \brief 线性控制寄存器位定义 */
#define UART_LCR_DLAB_POS         (7U)      /* 分频因子门闩访问位 */
#define UART_LCR_DLAB_MASK        (0x1U << UART_LCR_DLAB_POS)
#define UART_LCR_SPS_POS          (5U)
#define UART_LCR_SPS_MASK         (0x1U << UART_LCR_SPS_POS)
#define UART_LCR_EPS_POS          (4U)      /* 偶校验 */
#define UART_LCR_EPS_MASK         (0x1U << UART_LCR_EPS_POS)
#define UART_LCR_PEN_POS          (3U)      /* 校验位 */
#define UART_LCR_PEN_MASK         (0x1U << UART_LCR_PEN_POS)
#define UART_LCR_STB_POS          (2U)      /* 停止位 */
#define UART_LCR_STB_MASK         (0x1U << UART_LCR_STB_POS)
#define UART_LCR_WLS_POS          (0U)      /* 数据长度 */
#define UART_LCR_WLS_MASK         (0x3U << UART_LCR_WLS_POS)

#define UART_LSR_THRE_POS         (5U)
#define UART_LSR_THRE_MASK        (0x1U << UART_LSR_THRE_POS)
#define UART_LSR_DR_POS           (0U)
#define UART_LSR_DR_MASK          (0x1U << UART_LSR_DR_POS)

#define UART_FCR_RFIFOT_POS       (6U)
#define UART_FCR_RFIFOT_MASK      (0x3U << UART_FCR_RFIFOT_POS)
#define UART_FCR_TFIFOT_POS       (4U)
#define UART_FCR_TFIFOT_MASK      (0x3U << UART_FCR_TFIFOT_POS)
#define UART_FCR_DMAE_POS         (3U)
#define UART_FCR_DMAE_MASK        (0x1U << UART_FCR_DMAE_POS)
#define UART_FCR_TFIFORST_POS     (2U)
#define UART_FCR_TFIFORST_MASK    (0x1U << UART_FCR_TFIFORST_POS)
#define UART_FCR_RFIFORST_POS     (1U)
#define UART_FCR_RFIFORST_MASK    (0x1U << UART_FCR_RFIFORST_POS)
#define UART_FCR_FIFOE_POS        (0U)
#define UART_FCR_FIFOE_MASK       (0x1U << UART_FCR_FIFOE_POS)

#define UART_MCR_AFE_POS          (5U)
#define UART_MCR_AFE_MASK         (0x1U << UART_MCR_AFE_POS)
#define UART_MCR_LOOP_POS         (4U)
#define UART_MCR_LOOP_MASK        (0x1U << UART_MCR_LOOP_POS)
#define UART_MCR_RTS_POS          (1U)
#define UART_MCR_RTS_MASK         (0x1U << UART_MCR_RTS_POS)

#define UART_THR_THR_POS          (0U)
#define UART_THR_THR_MASK         (0xFFU)

#define UART_RBR_RBR_MASK         (0xFFU << UART_RBR_RBR_POS)
#define UART_RBR_RBR_POS          (0U)

/* \brief 分频门闩低 8 位寄存器位定义 */
#define UART_DLL_DLL_POS          (0U)
#define UART_DLL_DLL_MASK         (0xFFU << UART_DLL_DLL_POS)

/* \brief 分频门闩高 8 位寄存器位定义 */
#define UART_DLM_DLM_POS          (0U)
#define UART_DLM_DLM_MASK         (0xFFU << UART_DLM_DLM_POS)

/* \brief 过采样控制寄存器位定义 */
#define UART_OSCR_OSC_POS         (0U)
#define UART_OSCR_OSC_MASK        (0x1FU)

#define UART_IER_ERXIDLE_POS      (31U)
#define UART_IER_ERXIDLE_MASK     (0x1U << UART_IER_ERXIDLE_POS)
#define UART_IER_ERBI_POS         (0U)
#define UART_IER_ERBI_MASK        (0x1U << UART_IER_ERBI_POS)

#define UART_IIR_INTRID_POS       (0U)
#define UART_IIR_INTRID_MASK      (0xFU << UART_IIR_INTRID_POS)

#define UART_IDLE_CFG_RXEN_POS          (11U)
#define UART_IDLE_CFG_RXEN_MASK         (0x1U << UART_IDLE_CFG_RXEN_POS)
#define UART_IDLE_CFG_RX_IDLE_COND_POS  (9U)
#define UART_IDLE_CFG_RX_IDLE_COND_MASK (0x1U << UART_IDLE_CFG_RX_IDLE_COND_POS)
#define UART_IDLE_CFG_RX_IDLE_EN_POS    (8U)
#define UART_IDLE_CFG_RX_IDLE_EN_MASK   (0x1U << UART_IDLE_CFG_RX_IDLE_EN_POS)
#define UART_IDLE_CFG_RX_IDLE_THR_POS   (0U)
#define UART_IDLE_CFG_RX_IDLE_THR_MASK  (0xFFU)

/* \brief HPM 串口寄存器定义 */
typedef struct {
    volatile const uint8_t      RESERVED0[4];                /* 0x0 - 0x3: Reserved */
    volatile uint32_t           IDLE_CFG;                    /* 0x4: Idle Configuration Register */
    volatile uint32_t           ADDR_CFG;                    /* 0x8: address match config register */
    volatile uint32_t           IIR2;                        /* 0xC: Interrupt Identification Register2 */
    volatile uint32_t           CFG;                         /* 0x10: Configuration Register */
    volatile uint32_t           OSCR;                        /* 0x14: Over Sample Control Register */
    volatile uint32_t           FCRR;                        /* 0x18: FIFO Control Register config */
    volatile uint32_t           MOTO_CFG;                    /* 0x1C: moto system control register */
    union {
        volatile const uint32_t RBR;                         /* 0x20: Receiver Buffer Register (when DLAB = 0) */
        volatile uint32_t       THR;                         /* 0x20: Transmitter Holding Register (when DLAB = 0) */
        volatile uint32_t       DLL;                         /* 0x20: Divisor Latch LSB (when DLAB = 1) */
    };
    union {
        volatile uint32_t       IER;                         /* 0x24: Interrupt Enable Register (when DLAB = 0) */
        volatile uint32_t       DLM;                         /* 0x24: Divisor Latch MSB (when DLAB = 1) */
    };
    union {
        volatile uint32_t       IIR;                         /* 0x28: Interrupt Identification Register */
        volatile uint32_t       FCR;                         /* 0x28: FIFO Control Register */
    };
    volatile uint32_t           LCR;                         /* 0x2C: Line Control Register */
    volatile uint32_t           MCR;                         /* 0x30: Modem Control Register ( */
    volatile const uint32_t     LSR;                         /* 0x34: Line Status Register */
    volatile const uint32_t     MSR;                         /* 0x38: Modem Status Register */
    volatile uint32_t           GPR;                         /* 0x3C: GPR Register */
} hpm_uart_reg_t;


#define HPM_UART0   ((hpm_uart_reg_t *)HPM_UART0_BASE)
#define HPM_UART1   ((hpm_uart_reg_t *)HPM_UART1_BASE)
#define HPM_UART2   ((hpm_uart_reg_t *)HPM_UART2_BASE)
#define HPM_UART3   ((hpm_uart_reg_t *)HPM_UART3_BASE)
#define HPM_UART4   ((hpm_uart_reg_t *)HPM_UART4_BASE)
#define HPM_UART5   ((hpm_uart_reg_t *)HPM_UART5_BASE)
#define HPM_UART6   ((hpm_uart_reg_t *)HPM_UART6_BASE)
#define HPM_UART7   ((hpm_uart_reg_t *)HPM_UART7_BASE)
#define HPM_UART8   ((hpm_uart_reg_t *)HPM_UART8_BASE)
#define HPM_UART9   ((hpm_uart_reg_t *)HPM_UART9_BASE)
#define HPM_UART10  ((hpm_uart_reg_t *)HPM_UART10_BASE)
#define HPM_UART11  ((hpm_uart_reg_t *)HPM_UART11_BASE)
#define HPM_UART12  ((hpm_uart_reg_t *)HPM_UART12_BASE)
#define HPM_UART13  ((hpm_uart_reg_t *)HPM_UART13_BASE)
#define HPM_UART14  ((hpm_uart_reg_t *)HPM_UART14_BASE)
#define HPM_UART15  ((hpm_uart_reg_t *)HPM_UART15_BASE)

#ifdef __cplusplus
}
#endif  /* __cplusplus  */
#endif

